Who are the target users?
Space Codesign design tools are to
be used, in order of importance, by
the following specialized engineers
described below.
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Systems Engineer or Systems
Architects will clearly benefit
from Space Codesign™, because it
provides a global handle on the
systems. Architects can very easily
explore trade-offs for
hardware/software solutions by
partitioning the applications onto
architectures they can build, modify
and refine easily. They can obtain
performance monitoring results for
the overall system or for very
specific angles of a system.
It also links in simulating and
prototyping electronic systems.
Because Systems Engineers will often
have to work with FPGA prototypes
and other simulation tools, such as
Mathworks Simulink (Matlab), they
will quickly understand and take
benefits from the Space Codesign™
toolset and libraries.
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Software Engineers: since we
push software-oriented solutions, we
target Software Engineers to use our
toolset. Some may reply that SW
Engineers know little about
concurrency and parallelization, but
these concepts are clearly
encapsulated within the Space
Codesign™ environment and presented
as software real-time concepts, such
as rendezvous and message passing,
which are understood and mastered by
Software Engineers. Moreover,
software engineers have access to a
hardware model of the final target.
They can start codeing on the real
platform early in the design flow.
We believe that SW designers require
a brief introduction of the Space
Codesign™ concepts (as they would
for any other technology) to be
fully operational and drain the
maximum efficiency using this
technology.
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Hardware Engineers: Space
Codesign™ is an Electronic System
Level (ESL) toolset with which
Hardware Engineers will be asked to
interact more often with. Most of
the concepts found in hardware are
reproduced in Space Codesign, such
as concurrency. Moreover, the
SystemC language can be freely used
within the technology. SystemC
allows designers to either represent
their systems into SystemC HDL style
or C++ software style.
Because systems will rely more and
more on software in the next few
years, Space Codesign™ will allow
hardware designers to easily
interface with the software parts of
a system.
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What about behavioral or C, C++ or SystemC
synthesis?
Space Codesign Systems software does not
do behavioral synthesis. We
support a component substitution methodology,
taking a SystemC
TLM component and replacing it
with an VHDL/Verilog IP, all taken
from libraries of component we, you or
third-parties provide. Space Codesign Systems' GenX generates
custom blocks dedicated for handling
communications throughout on-chip components
as well as basic system functions. Because our
software is linked to FPGA design
and prototyping tools, we are able
to export a system built in
SpaceStudio to software such as
Xilinx Platform Studio and EDK,
aiming the Xilinx FPGA technology.
FPGA are used either as prototyping
boards to full ASIC solutions, or as
final chips to be embedded.
Additionally, we offer links to existing behavioral
synthesis tools to convert
C, C++ or SystemC blocks into hardware
synthesizable or pre-synthesizable
blocks. The tools we currently support are:
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Cynthesizer from Forte Design Systems
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CatapultC from Mentor Graphics
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Because Space Codesign Systems target and
promote the use of software into
embedded systems, all software
developed in SpaceStudio is exported
and directly reusable as target code.
What are the time savings from
using TLM or Space Codesign Systems models ?
Several advantages exist from using
C-based designs, here is a short
list.
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Validate your applications in a fully supported software environment;
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Increase System Design Productivity;
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Reduce Development & Maintenance Costs and
Turnaround Time;
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High-Level Specification and
Simulation (C, C++, SystemC);
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Work on software and acknowledge Performance Criteria
before any physical Hardware is Ready
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System Validation Eliminates
unwanted surprises as the final
system is integrated;
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What is offered by Space Codesign
that SystemC does not already
provide?
It is important to understand that
SystemC is a library added to C++
for hardware description. No support
for software, except the C++
language itself, is provided,
abandoning the user with the
complicated task of modeling real
software behavior.
Space Codesign Systems brings a framework usable through
guided steps to help users build
proper systems very quickly.
Moreover, it is a virtual platform
that brings all the support required
for RTOS-based software modeling.
More exhaustively, we
enhance the SystemC functionality by:
Creating
a framework for system design
Guidelines for efficient module
construction;
Libraries for common components such
as bus, timed or not, ISS,
peripherals
Multiprocessor Systems-on-Chip
Performance analysis and monitoring;
Creating
a Software Simulation Environment
Host-processor Software Simulation
ISS based on
cycle approximate processor models (ARM,
PowerPC, ...)
Integrated RTOS (task preemption,
thread scheduling, priority
assignment, etc.)
How do you differentiate from
competition?
In a technical way, our main and true
differences are:
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We simplify the introduction, programming and maintenance of software-based or software-supported
systems into typical FPGA hardware designs.
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We propose true multiprocessor simulation, debugging and analysis.
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We offer automated
hardware/software architectural exploration capabilities and analysis; not
limited to a graphical interface for
instantiating and connecting
components
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We offer an automated down-to-the-chip mechanism that allows fast target
prototyping on FPGA.
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What are the simulation
performance gains?
The following numbers are
estimations based on testbenches and on-field designs we have built, and are taken
from literature.
click to enlarge picture
We must keep in mind some facts :
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Hardware user modules must be
represented in the proper
abstraction level (timed fuctional versus
RTL); otherwise, the simulation
speedup is not as effective as it could be.
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Communication performance gain from
timed functional to bus cycle
accurate is about 10X. Comparison to RTL typical
simulation is 100X and more.
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We can hit over 20M
channel transactions per simulation
wall-clock second for timed
functional simulations and 250k
transactions per second for
simulation integrating an
instruction set simulator. Which is comparable
to all other ISS and comparable to our competitors.
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Do you offer a verification
strategy?
SpaceStudio does not directly
provide specific features for
verification. Though SystemC SCV, a verification standard extending SystemC aiming at being
the industry's premier testbench language. You can integrate SCV into SpaceStudio and all Space Codesign Systems
softwares.
What is the difference between
SystemC, SystemVerilog and SpaceStudio/SpaceCodesign?
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SystemVerilog is clearly an addition
to Verilog for enhanced HDL support
and verification support.
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SystemC is a C++ add-on library used
to model hardware components. It
offers additional support for
transaction level modeling, model
verification, and support for
master-slave communication paradigm.
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Space Codesign Systems offers a toolset based
on SystemC to create, map,
analyze and simulate SW/HW systems. Users can insert C or C++ functions as software code.
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Could I use SystemVerilog
with your platform?
No. You do not find in SystemVerilog the
support for software-based systems,
such as threads, which is vital for
software simulations.
The language is based on the former
Verilog, still very oriented towards
hardware description (bits,
processes, etc.), where the
description is heavy and long, not
properly abstracted and not suited
for system level design.
Can I import my legacy C/C++ or even SystemC?
Yes.
First, all C, C++ or SystemC models
can be easily integrated, as we
propose generic wrapper that only
requires your code, functions or
basic blocks to be
imported into the
SpaceStudio environment. We
offer a application programming
interface (API) to open your code to
the design framework. This API will
allow, for instance, to let your
functions to exchange information.
Space Codesign Systems can easily
integrate your own IPs, whether they
are communication channels, busses,
peripherals or hardware
accelerators, co-processors,
processors (instruction set
simulators). Integrating your
components into Space Codesign
includes:
making them compatible with SpaceStudio,
which reads
and understands your components;
hooking them to the monitoring
engine;
making their design interface to be
compatible, so they can communicate
on our design platforms.
Space Codesign offers two sets of
components: SpaceBaseModules, which
can be seen as parts of your
application. These components will
especially be seen by the
partitioning engine, and drag'n drop
partitioning of these components
will be possible. SpaceBaseDevice
are slave components, for instance a
FFT as a co-processor, which will
not be part of exploration. Your
components can be imported into one
of these possibilities.
The Space Codesign toolset, as it
exists today, works with the XilinxTM
technology and the IBM CoreConnectTM
platform. Integrating new components
that support these protocols is made
through SpaceStudio. Please contact
us for possibilities and
availabilities of our staff.
Which platforms and IP are currently supported ?
The following IP and models, either SystemC or VHDL
are available now for sales:
IBM CoreConnectTM platform, including
the CoreConnectTM OPB, PLB and DCR
and the IBM PowerPCTM;
Xilinx Virtex-IITM, Virtex-II ProTM
Virtex-IVTM and Virtex-5TM FPGA devices.
The Space Codesign Systems software can be
applied to different technologies,
including other FPGA vendors, ASIC,
ASIP, multi-processor development
environments (see
Design Methodology FAQ). Also other simulation
models can be developped, including
ARM/AMBA processors/protocols,
Altera devices, OCP or your own
specific models. Please
contact
the sales department for inquiries
related to custom development.
What domains of applications the Space Codesign Systems technologies apply to?
Because it offers very high speed of
simulation with progressive steps down
to a final implementation, we can think
of any high speed requirements and data-oriented
applications :
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Telecommunication;
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Video and audio processing;
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Imaging, CCTV controllers.
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Because we offer the possibility to
integrate support of Real-time
Operating Systems (RTOS), we can
think of any domain which is under
hard real time constraints :
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Automotive and Transport (trains);
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Reactive Systems and controllers
(engines);
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How can I integrate my VHDL/Verilog legacy IP into your environment ?
Do some text.
