GENX
SpaceStudio helps users create virtual platforms very quickly by dragging and dropping components from an existing library. These system configurations containing processors, busses, and peripherals can be exported to (e.g.) Xilinx FPGA design and implementation tools, to realize initial prototypes, or first to final silicon.
Space Codesign‘s GenX technology substitutes all architectural models with pre-existing implementable components, cross-compiles the target code for every processor, and generates all RTL blocks for message routing, memory mapping, interfaces and wrappers for hardware-partitioned blocks.
Hence, Space Codesign™ technology will let you go ...
... in just a few mouse clicks!
A
3-step automated synthesis process
Space Codesign‘s technology performs an automated hardware/software co-synthesis process in 3 steps:
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Software generation is completely automatic. User software tasks and RTOS are compiled for the selected embedded processor. For instance, SystemC function calls are mapped to RTOS equivalents and then Space Codesign‘s Tor technology transforms hardware behaviors into software ... and vice-versa!
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Hardware synthesis is accomplished using a third-party high-level synthesis (HLS) tool such as ForteDS Cynthesizer or Mentor Graphics CatapultC (when C syntax allows). Should you not have access to these powerful tools, wrappers using a predefined interface are generated to let you connect your IP to the generated RTL platform.
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Communications synthesis is also achieved. In the case of targeting Xilinx FPGA technology, RTL IP wrappers called IPIF (Xilinx Intellectual Property InterFace) are be automatically generated using the Xilinx Import Peripheral Wizard. Ultimately, GenX generates the optimum platform partitioning in two files that are input into Xilinx Platform Studio: one contains C-code and RTOS-specific function calls cross-compiled for a target processor (Xilinx MicroBlaze® or IBM PowerPC®, for example), while the other file contains a list of IPs and processors along with their connections to the different busses that are instantiated.
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Supported
technology
We currently support Xilinx Virtex-II, Virtex-II Pro and Virtex-IV and Virtex-V families of FPGA and we can extend the Space Codesign™ library, SpaceLib, to other technologies, upon request.
Support for ARM Cortex A is under development.
