GENX

SpaceStudio lets user create virtual platform very quickly by dragging and dropping components from an existing library. Therefore, system configurations containing processors, busses, and peripherals can be exported to Xilinx FPGA design and implementation tools, to continue on with on-chip first prototypes or final solution debugging.

The Space Codesign™ technology substitutes all architectural models with pre-existing implementable components, cross-compiles the tagret code for every processor, and generates all the RTL mechanic for message routing, memory mapping, interfaces and algo generates wrappers for hardware-partitionned blocks.

Hence, Space Codesign™ technology will let you go:

 

 

A 3-step automated synthesis process

The Space Codesign™ technology performs an automated hardware/software co-synthesis process in 3 steps:

	Software generation is completely automatic. The user software tasks and the RTOS are compiled for the selected embedded processor. For instance, the SystemC function calls are mapped to RTOS equivalents and with the Space Codesign™ Tor technology, which re-implements some hardware behaviors in software.
	Hardware synthesis is accomplished using a third-party behavioral synthesis tool, such as ForteDS Cynthesizer or Mentor Graphics CatapultC (when C syntax allows). Should you not have access to these powerful tools, Wrappers using a predefined and effective interface are generated to let you connect your IP to the generated RTL platform.
	Communications synthesis is also processed. Using the Xilinx technology, RTL IP wrappers called IPIF (Xilinx Intellectual Property InterFace) are be automatically generated using the Xilinx Import Peripheral Wizard. Ultimately, Gen X generates the optimum platform partitioning in two files input into Xilinx Platform Studio: one contains C-code and RTOS-specific function calls cross-compiled for processor (Xilinx MicroBlaze® and/or IBM PowerPC® for instance), while the other file contains a list of IPs and processors along with their connections to the different buses instantiated.

Supported technology

We currently support Xilinx Virtex-II, Virtex-II Pro and Virtex-IV and Virtex-V families of FPGA and we can extend the Space Codesign™ library to other technologies, upon request.